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Home - Global Tech Pulse - PJON, Open Single-Wire Bus Protocol, Goes Verilog
Global Tech Pulse

PJON, Open Single-Wire Bus Protocol, Goes Verilog

NextTechBy NextTechDecember 13, 2025No Comments2 Mins Read
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Did OneWire of DS18B20 sensor fame ever fascinate you in its single-data-line simplicity? If that’s the case, then you definately’ll like PJON (Padded Jittering Operative Community) – a single-wire-compatible protocol for as much as 255 units. One drawback is that you must inspect the bus fairly usually, buying and selling {hardware} complexity for software program complexity. Now, that is now not one thing for the gate wielders of us to fret about – [Giovanni] tells us that there’s a {hardware} implementation of PJDL (Padded Jittering Knowledge Hyperlink), a PJON-based bus.

This implementation is written in Verilog, and permits you to offload plenty of your low-level PJDL duties, primarily, providing you with a PJDL peripheral for all of your inter-processor communication wants. Oh, and as [Giovanni] says, this module has just lately been taped out as a part of the CROC chip mission, an academic SoC mission. What’s to not love?

PJON is a enjoyable protocol, quickly to be a decade outdated. We’ve beforehand coated [Giovanni] use PJON to determine an information hyperlink by means of a pair of LEDs, and it’s good to see this nifty small-footprint protocol acquire that rather more of a foothold, now, in our hardware-level tasks.

We thank [Giovanni Blu Mitolo] for sharing this with us!

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